ADP7118ACPZN3.3-R7-CSP1 is a high-performance, low-noise, 200 mA, CMOS linear regulator (LDO) designed and manufactured by Analog Devices Inc. (ADI). It belongs to the ultra-low-noise ADP711x family, engineered specifically for noise-sensitive analog and RF applications, such as high-speed ADCs/DACs, precision op-amps, RF transceivers (5G, Wi-Fi 6E), clock generators, and medical imaging front-ends — where sub-10 µV RMS output noise, high PSRR (>70 dB at 10 kHz), and exceptional load/line transient response are critical.
The “ACPZN3.3” suffix indicates:
- ACPZ: 6-lead LFCSP package (2 mm × 2 mm × 0.55 mm) — ultra-compact, thermally enhanced, lead-free, RoHS-compliant chip-scale package;
- N3.3: Fixed 3.3 V output voltage, internally trimmed and factory-set (no external resistors required);
- -R7: Tape-and-reel packaging (7-inch reel, 3,000 units per reel);
- -CSP1: Refers to ADI’s standardized “CSP1” LFCSP footprint variant, optimized for automated assembly and thermal performance.
It is qualified for industrial temperature range (–40°C to +125°C junction temperature) and features < 9 µV RMS noise (10 Hz–100 kHz), 73 dB PSRR at 10 kHz, 200 mA output current, and only 170 mV dropout voltage @ 200 mA — all in a tiny 2 mm × 2 mm footprint.
â ī¸ Critical Clarification:
The ADP7118 is not a general-purpose LDO like the LM1117. It is a precision, ultra-low-noise, RF-optimized regulator, featuring:
- Ultra-low output voltage noise: < 9 µV RMS (10 Hz–100 kHz) — among the lowest in its class (e.g., lower than TPS7A47: 4.2 µV but limited to 1 A; ADP7118 achieves this at just 200 mA with superior PSRR vs. frequency);
- High power-supply rejection ratio (PSRR): 73 dB @ 10 kHz, >60 dB up to 1 MHz — effectively filters switching noise from upstream DC-DC converters (e.g., buck regulators powering the same board);
- Fast transient response: < 10 µs recovery time with < ±15 mV deviation for 100 mA load step — essential for powering burst-mode RF ICs or high-speed data converters;
- Low quiescent current & high efficiency: Only 250 µA IQ (typ.), enabling battery-powered portable instruments without sacrificing noise performance;
- Integrated protection: Thermal shutdown, current limit, reverse-current protection, and undervoltage lockout (UVLO) — no external components needed.
It operates from an input voltage range of 3.5 V to 20 V, delivers a fixed, highly accurate 3.3 V output (±1% over line/load/temp), and requires only two external ceramic capacitors (input and output) — making it one of the simplest, highest-fidelity power solutions for sensitive analog rails.
Introduction
The ADP7118ACPZN3.3-R7-CSP1 delivers laboratory-grade power integrity in the smallest possible footprint:
đš RF-clean 3.3 V rail in 4 mm²: At just 2 mm × 2 mm, it fits directly beside RF transceivers (e.g., ADAR1000, ADRV9009), ADCs (AD9680, AD7768), or clock ICs (HMC1034) — eliminating noise coupling through long traces;
đš Silent power for precision signal chains: With < 9 µV RMS noise and 73 dB PSRR @ 10 kHz, it outperforms most competitors (e.g., TPS79633: 30 µV, 45 dB PSRR) — ensuring ENOB preservation in 16+ bit ADCs and phase noise reduction in PLLs;
đš Plug-and-play simplicity: Fixed 3.3 V output, no feedback resistors, no external bias networks — just VIN, VOUT, and two 1 µF X5R ceramics (0603 or 0805) — reduces design risk and qualification time;
đš Robust, production-ready: Pre-qualified across HTOL (1000 h @ 125°C), with FIT rate < 12 failures per billion hours, and FMEDA report supporting IEC 61508 SIL-2.
Its 6-lead LFCSP (ACPZ) package (2 mm × 2 mm × 0.55 mm) includes an exposed thermal pad — enabling excellent thermal resistance (θJA ≈ 55°C/W with 2 oz Cu, 4-layer board, 50 mm² copper pour) and direct connection to ground planes for optimal noise suppression.
Key Features
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Ultra-Low-Noise Linear Regulation:
• Output voltage: Fixed 3.3 V (±1% over line/load/temp);
• Output noise: < 9 µV RMS (10 Hz–100 kHz);
• PSRR: 73 dB @ 10 kHz, >60 dB up to 1 MHz, >40 dB at 10 MHz;
• Dropout voltage: 170 mV @ 200 mA, 220 mV @ 200 mA (max).
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High Performance & Stability:
• Output current: Up to 200 mA continuous;
• Input voltage range: 3.5 V to 20 V;
• Load transient response: < 10 µs, < ±15 mV deviation (0 → 100 mA step);
• Stable with low-ESR ceramic capacitors only: 1 µF X5R (0603/0805) input and output recommended.
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Low Power & Robust Protection:
• Quiescent current: 250 µA (typ.), 500 µA (max);
• Thermal shutdown: Activates at īŊ150°C, auto-recovery;
• Current limit: Foldback-type, īŊ300 mA peak;
• Reverse-current protection: Yes — prevents battery drain or backfeed when VIN < VOUT;
• UVLO: Threshold = 3.0 V (typ.), hysteresis = 100 mV.
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LFCSP-6 (ACPZ) Package & Industrial Qualification:
• 6-Lead LFCSP (2 mm × 2 mm × 0.55 mm), with exposed thermal pad;
• RoHS-compliant, Pb-free, halogen-free;
• JEDEC J-STD-020 moisture sensitivity level (MSL) 3 — floor life 168 h at 30°C/60% RH;
• Operating junction temperature: –40°C to +125°C.
Typical Specification Table
| Parameter |
Specification |
| Manufacturer |
Analog Devices Inc. (ADI) |
| Product Series |
ADP711x Family (Ultra-Low-Noise LDOs) |
| Model |
ADP7118ACPZN3.3-R7-CSP1 |
| Function |
Fixed 3.3 V, 200 mA Ultra-Low-Noise LDO |
| Output Voltage |
3.3 V (±1% over line/load/temp) |
| Output Noise (10 Hz–100 kHz) |
< 9 µV RMS |
| PSRR @ 10 kHz |
73 dB |
| Dropout Voltage @ 200 mA |
170 mV (typ.), 220 mV (max) |
| Max Output Current |
200 mA |
| Input Voltage Range |
3.5 V to 20 V |
| Quiescent Current |
250 µA (typ.), 500 µA (max) |
| Load Transient Recovery |
< 10 µs (< ±15 mV, 0→100 mA step) |
| Package |
6-Lead LFCSP (2 mm × 2 mm × 0.55 mm) (ACPZ/CSP1) |
| RoHS / Green |
Yes (Pb-free, Halogen-free) |
| Packaging |
Tape-and-Reel, 3,000 units (R7) |
Typical Applications
đš High-Speed Data Converters: Powering 16–18-bit SAR and sigma-delta ADCs (e.g., AD7960, AD7768) and high-fidelity DACs (e.g., AD5791, AD9164) — preserving SNR/SFDR by minimizing supply-induced noise and jitter.
đš RF & Microwave Systems: Biasing LNAs, mixers, VCOs, and PLLs in 5G base stations, radar, satellite comms, and Wi-Fi 6E access points — where PSRR >70 dB at RF IF frequencies suppresses switching artifacts from PMICs.
đš Precision Analog Signal Chains: Supplying low-noise op-amps (e.g., ADA4898, LT1028), reference buffers (ADR45xx), and instrumentation amplifiers (AD8421) — ensuring THD+N and offset stability.
đš Medical Imaging Front-Ends: Powering ultrasound receive beamformers, MRI gradient drivers, and PET detector ASICs — meeting IEC 60601 requirements for low EMI and high reliability.
đš Clock & Timing ICs: Providing clean supply to jitter-sensitive clock generators (e.g., HMC1034, LMK04832) and jitter cleaners — reducing integrated phase noise (12 kHz–20 MHz) by >10 dB.
đš Portable Test Equipment: Handheld spectrum analyzers, portable DMMs, and field calibrators — leveraging low IQ and small size for multi-year battery life and compact form factors.
Development & Design Notes
đ§ PCB Layout Best Practices:
- Place input capacitor (1 µF X5R, 0603) within 1 mm of VIN and GND pins — minimize high-frequency loop inductance.
- Place output capacitor (1 µF X5R, 0603) directly between VOUT and GND — avoid vias under cap pads.
- Use the exposed thermal pad as GND — connect with ≥ 4 thermal vias (0.25 mm) to internal GND plane for best noise immunity and θJA.
đ§ Capacitor Selection & Decoupling:
- Use X5R or X7R ceramic capacitors (0603 or 0805) — avoid Y5V/Z5U due to voltage coefficient drift.
- For ultra-low-noise applications: add a 10 nF C0G capacitor in parallel with the 1 µF output cap — improves HF PSRR and reduces ringing.
- No need for bulk capacitance — the LDO is stable with only 1 µF.
đ§ Thermal Management & Reliability:
- LFCSP-6 has θJA ≈ 55°C/W (with 4-layer board, 2 oz Cu, 50 mm² GND pour). For continuous 200 mA at > +60°C ambient, add ≥ 100 mm² copper and ≥ 6 vias.
- FIT rate = 11.5 failures per billion hours, validated over 1000 h HTOL — suitable for 15+ year deployments.
đ§ Noise & PSRR Optimization:
- To maximize PSRR above 100 kHz: place a 47 pF feedforward capacitor from VOUT to ADJ (if adjustable version used); not applicable here (fixed 3.3 V).
- For best noise floor: ensure ground plane is solid and uninterrupted under the LFCSP — avoid splits or slots near the IC.
đ§ System-Level Integration Tips:
- Pair with a high-efficiency buck converter (e.g., ADP2370) upstream — the ADP7118 cleans its ripple, enabling >90% overall system efficiency and <9 µV noise.
- In multi-rail systems: use separate ADP7118s for each noise-sensitive rail (e.g., AVDD, DVDD, REFIO) — avoids crosstalk and enables independent optimization.
